1. Field of the Invention
The invention relates generally to electronic circuitry and more particularly to digital circuit design techniques in semiconductor devices resulting in the limiting of ground bounce.
2. Description of the Prior Art
CMOS chip suppliers are plagued by momentary undulations of ground (Vss) potential called "ground bounce." Abrupt discharges of large doses of current to ground are attributable to the tremendous pulldown action of output buffers; these buffers sink the charge coming from the output loads through a chip's internal ground path which terminates in an unavoidable series inductance to system ground.
Both faster switching speeds and higher current sinking ability exacerbate ground bounce. Too severe a ground bounce will cause false level transitions in both the driving and driven devices. Less severe ground bounce will decrease noise immunity, because positive ground bounce robs from Voltage Input High (VIH) margins and negative ground bounce cuts into Voltage Input Low (VIL) margins.
Ground bounce effects are sensitive to process, temperature, and operating voltage variations. "Fast" process, low temperature, and high operating voltage each increase ground bounce. Device speed, a dominant parameter, is worst at the opposite extremes: slow process, high temperature, and low operating voltages. Testing for speed receives so much attention at its worst case extremes, that the worst case extremes for ground bounce are often ignored.
Prior art has attempted to correct ground bounce. Each attempt uses a different approach, but all achieve less that a complete solution. Invariably, a common technique employed involves distributing the current running through pulldown devices. Multiple pulldown devices each handle a reduced portion of the whole current and are successively turned on via a delay chain.
Consider the prior art of FIG. 1 discussed in U.S. Pat. No. 4,785,201 by Martinez. The circuit of FIG. 1 uses a P-type Metal Oxide Semiconductor (PMOS) pullup transistor 110 and a N-type Metal Oxide Semiconductor (NMOS) pulldown transistor 112 as a pair of strong driving elements. (The parasitic, but "unavoidable series inductance to system ground" is shown as a discrete inductor 184, and a matching inductor 180 to Vcc.) A PMOS pullup transistor 114 and a NMOS pulldown transistor 116 form a pair of weak driving elements. The weaker pair are designed to turn on prior to the stronger pair via delays introduced by a pair of inverter transistors 118 and 120. The main idea is that the large current spike created when a large lumped device is turned on will be decreased in intensity if a previously activated weaker device dissipates some of the initial discharge energy. The gain of the stronger devices can be slightly lower than would otherwise be required.
The U.S. Pat. No. 4,638,187, Boler et al, suggests the prior art circuit of FIG. 2. The circuit in FIG. 2 differs from that in FIG. 1 in the implementation of the pulldown action. Instead of using a PMOS pulldown as a weaker device, another NMOS pulldown transistor 94 is used instead. This weaker pulldown transistor 94 has a smaller gain than the main NMOS pulldown 96. The delay is introduced by an R-C network that includes a resistor 98 (and stray capacitance), instead of an inverter chain.
The circuit contained in U.S. Pat. No. 4,777,389 by Wu et al is repeated in prior art FIG. 3. This circuit essentially uses the same current distribution of the two examples above, but uses a different method of achieving the delay for the second, stronger pulldown transistor. (The stray inductance-resistance to system ground is shown as discrete devices an inductor L2 and a resistor R2, and a matching pair of an inductor L1 and a resistor R1 to Vcc.) The delay in turning on the second, stronger pulldown transistor results from a closed loop control that waits for the high to low transition of the output on a line 50 to reach a certain level before a pulldown transistor 118 is activated. This assures an adequate time spacing between the two current spikes.
None of the prior art above directly monitor or control the particular electrical parameter that results in ground bounce, namely, the time rate of change of the pulldown current (di/dt). The sensitivities to process, temperature, and operating voltage also go largely neglected.
The prior art of FIG. 4, U.S. Pat. 4,622,482, Ganger, directs itself to limiting the output voltage slew rate in telecommunications applications. Referring to FIG. 4, a pair of fixed capacitors 18 and 32, and a pair of constant current sources 20 and 40, are each used to perform slew rate limiting and to insure linearity.
Several undesirable consequences result from the implementation of FIG. 4. Biasing circuits are required to provide N-bias and P-bias potentials, thereby requiring an accurate source externally and therefore extra I/O pins. Alternatively, internally generated biases would necessitate generators with large static DC currents to sustain a reasonable noise rejection ratio.
In the circuit of FIG. 4 a complementary pair of push-pull transistors 14 and 30 are never mutually exclusive because their gates are not pulled completely up to Vdd or down to Vss when intended to be off. This results in large leakage currents that are usually unacceptable in digital circuits. And since the push-pull transistors 14 and 30 are never quite off, parasitic capacitive coupling in their gates to Vdd and Vss will cause the push-pull transistors 14 and 30 to amplify any high-frequency noise on the Vdd and Vss supply rails.
Slew-rate control is confined only to the saturation region of the output transistors 14 and 30 when static biasing is used. Since the value of capacitors 18 and 32 do not change to accommodate the push-pull transistors 14 and 30 transition from their saturation region to their linear region, the linearity control fails at this stage and throughout the linear region of operation.
The capacitive coupling provided by capacitors 18 and 32 will couple any output transition back to the gate of the supposedly off transistor 14 or 32 to cause it to turn on. While the resulting current contention has the effect of further limiting the voltage slew rate of the output 16, it inadvertently dumps even more transient and DC current to Vss, which actually increases ground bounce in digital circuits.
The circuit of FIG. 5 (which originates from a pending application, Ser. No. 07/300,915, by Leung et al., and assigned to the assignee of the current application) corrects some of the deficiencies of the circuits discussed above. The circuit of FIG. 5 assumes that the current sourced by a pair of transistors 170 and 172 is constant--which it is not. As a result, a superposition of higher order voltage functions of "t" (time) on a line 182 occurs; and that effectively subverts the square-root-of-t relationship that is critical to promoting the proper slew-rate limiting needed to suppress ground bounce.
A transistor 190 in FIG. 5 is supposed to provide additional drive to the gate of a transistor 196. This additional drive is needed to initially boost the voltage on line 182 from zero to VT. But, transistor 190 is switched off too late, because the output of a gate 152 on a line 158, which are connected to the input gate of transistor 190, transitions sometime after the greatest rate of change in the pulldown current has already been reached in transistor 196.
The circuit of FIG. 5 allows a capacitor node, which exists on the gate of the pulldown transistor 196, to charge all the way down to zero, thus inhibiting a jump to VT potential at the onset of the pulldown action of transistor 196. It has been determined that it is of prime importance to have a node, such as line 182, jump to VT potential at the onset of the pulldown action. The VT shift is essential to maintaining an optimum speed to ground bounce ratio, but it is absent in the prior art.